1. Field of the Invention
The present invention relates to processes for forming dielectric film blocks over resistor areas during semiconductor manufacturing. More particularly, the present invention relates to the use of block dielectric layers over selected poly and island resistors to prevent silicidation.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
One of the common additional operations involves the reduction of interconnect resistance. A self-aligned silicide (salicide) operation provides low resistance source drain connections as well as low-resistance polysilicon contact areas. In conventional CMOS processing, salicided metal contacts are initially formed on silicon substrates by depositing cobalt, titanium or other metals and then annealing. Silicides, such as tungsten silicide (WSi2), titanium silicide (TiSi2), and cobalt silicide (CoSi2) are used in the semiconductor industry to enhance signal propagation through MOS transistors and other conductive features of semiconductor devices. A conventional silicide process produces a low resistance silicide region on the top of an MOS transistor""s polysilicon (xe2x80x9cpolyxe2x80x9d) gate electrode and interconnect. The suicide has a lower resistance than the underlying doped silicon or poly. As a result, signal propagation through the transistor (gate and interconnect) is enhanced.
While salicide formation may be desirable to reduce interconnect resistance in active devices, it is undesirable in applications where resistors are formed on the wafer. Both active and passive (i.e., capacitors and resistors) components are commonly found on semiconductor wafers. During the salicidation processes, salicide blocks are used to mask the resistor areas from the silicide film, thus maintaining the high resistance characteristics of the poly or other type of resistor.
Conventional salicide block processes deposit a relatively thick (e.g., 400 Angstrom) low temperature oxide (LTO) layer over the wafer. A block mask layer is then patterned to protect the selected resistor areas. Exposed areas are then etched using a timing etch to allow a thin (e.g., 100-200 A) oxide to remain on the active areas. Timed etches, however, are difficult to control from lot to lot, from chamber to chamber, and even across the width of the wafers. Likewise, control problems exist also in the salicide preclean step where typically an HF etch is performed prior to silicide formation to remove all oxide over the active areas. Namely, the salicide preclean operation has a low etch margin. Too long an overetch will remove block oxide from the masked areas and/or the field oxide areas while too short an over etch will cause incomplete salicidation.
Accordingly, it is desirable to provide a more effective salicide block process which has a greater process marginality. A desirable dielectric block mask process would allow all non-block area oxides to be removed in order to form a high quality salicide but would also allow oxide to remain on the resistor block area to prevent silicide formation. Further, a desirable dielectric block mask process would minimize removal of oxide from field oxide areas.
To achieve the foregoing, the present invention provides a salicide block process which uses Si3N4 or SiON as the block dielectric film. A block dielectric film is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a block dielectric film layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide film serves as an etch stop layer during etching of the block dielectric film and also reduce the stress between SiN (SiON) and Si.
In one embodiment, the present invention provides a method of forming a block dielectric film to protect selected areas of a semiconductor wafer from a silicide process. Initially a low temperature oxide film is provided on the wafer. A block dielectric film comprising Si3N4 or SiON is disposed on the low temperature oxide film. A mask is formed over the selected areas, such as the resistor locations, and patterned so that the selected areas are covered by the mask during the etching operation which follows. During the etching operation of the unmasked areas, an etchant is selected so that the etching of the block dielectric film stops on the low temperature oxide film. The block mask is then removed and exposed portions of the oxide layer are removed in a salicide preclean operation. A silicide is then formed on the exposed areas of the semiconductor wafer, i.e., those areas comprising silicon and polysilicon.
In another embodiment, the etchant chemical for the block dielectric film is selected so that it has a selectivity of about 10:1 or greater Si3N4 or SiON to the oxide layer.